This invention is in the field of integrated circuit manufacturing, and is more specifically directed to photolithography processes in such manufacturing. As is fundamental in the field of integrated circuit electronics, the functional capability of an integrated circuit depends substantially upon the number of active components (transistors, resistors, capacitors, etc.) that can be physically realized per unit area of the integrated circuit. It is therefore desirable to fabricate device features that are as small as possible, and as closely packed as possible, to provide not only a high level of functionality for the integrated circuit, but also a high level of circuit performance due to such small feature sizes. For example, many modern integrated circuit devices are fabricated with lateral features that are below one-half micron in width, realizing as many as tens of millions of transistors in a single integrated circuit operating at clock frequencies greater than 100 MHz. It is contemplated that these trends toward smaller and faster devices will continue, to the extent permitted by the state of the art of the manufacturing technology.
Conventional integrated circuit manufacturing technology utilizes photolithography for defining the location and dimensions of lateral features in the integrated circuit. As is fundamental in the art, photolithography is generally carried out by the application of a photosensitive substance, referred to as photoresist, over the film to be patterned. Selective exposure of the photoresist to electromagnetic energy (i.e., light) defines the portions of the film that are to be removed by the developing process, and those locations that are to remain. For purposes of manufacturing efficiency, the photoresist over the full area of one or more of the integrated circuits on the wafer are simultaneously exposed through photomasks, with transparent and opaque regions of the photomasks defining the locations of the photoresist that are exposed or not exposed, respectively. As a result of developing, photoresist is removed from the surface of the wafer, with the remaining regions of the photoresist (as defined by the selective exposure) serving as a mask to the etch of the underlying film, thus defining the features of the integrated circuit. Such masking may also be used in connection with other processes, such as ion implantation. Once the etch is completed, the remaining photoresist mask is then removed from the wafer. The processing of the wafer continues, with deposition of the next film layer and, if desired, photolithographic patterning and etching of this next layer.
According to modern conventional technology, the photomasks are generally in the form of reticles, where the images on the photomask itself are of some multiple magnitude (e.g., 4X) of the feature size to be patterned on the wafer. Exposure of the wafer through the reticle is carried out in combination with a focusing lens system disposed between the reticle and the wafer, so that the patterned exposure is reduced from that on the reticle. Reticles are generally used in connection with stepper exposure systems, in which only one or a few integrated circuit die are exposed at a time; the wafer is then indexed, or xe2x80x9csteppedxe2x80x9d, to the next position for photo-exposure through the reticle. The larger feature sizes on the reticles, relative to the integrated circuit feature sizes, facilitates the fabrication of the reticles themselves by way of photolithography. Of course, the photomasks may alternatively be so-called 1xc3x97photomasks that are placed in proximity to the wafer being patterned. For purposes of this description the term photomask will refer both to 1xc3x97photomasks and also to reticles, of both the full wafer and stepper type.
Certain xe2x80x9ccritical dimensionxe2x80x9d features in the integrated circuit, such as transistor gate electrodes, contact aperture sizes, and conductor widths and the like, relate directly to the density and performance of the integrated circuit. Typically, minimum width transistor gate electrodes are the most critical features in the integrated circuit layout, given the prevalence of transistors in the integrated circuit and also considering that gate electrode width relates directly to transistor channel length and thus to the gain and switching speed of the device. As such, the ability to reliably define and construct ever-smaller features such as transistor gates is of high importance in the field of integrated circuit design and manufacture.
As noted above, critical dimension features of modern integrated circuits are now on the order of one-half micron or less. Such sub-micron critical dimensions are on the order of the wavelength of the light energy used in the exposure. At these dimensions, the minimum feature size that may be imaged, at a usable depth of focus, depends strongly upon the wavelength of light used; so-called xe2x80x9cdeep UVxe2x80x9d light is currently used to effect the higher resolution imaging required for modern integrated circuits. In modern photolithography processes, the minimum feature size that may be imaged by a photomask is approximately       0.5    ⁢          λ      NA        ,
where xcex is the wavelength of the exposing light and NA is the numerical aperture of the lens system of the stepper. The proportionality constant of this resolution ratio (in this example, having the value 0.5) is commonly referred to in the art as k1; a similar relationship is provided for depth of focus (having a proportionality constant k2). While a large numerical aperture permits the patterning of extremely small features, the depth of focus of the lens system decreases with increasing NA values. Considering the realistic extent to which the topography of the wafer can be made flat during its manufacture, which in turn limits the numerical aperture of the lens system, the minimum feature size that can be patterned by photolithography at a given wavelength reaches a practical limit.
Certain techniques for further reduction in the feature size that may be imaged for a given wavelength are also known in the art. One known technique uses a phase-shift photomask in which adjacent or nearby openings, or apertures, transmit light at opposing phases (i.e., 0xc2x0 and 180xc2x0). As known in the art, light passing through a mask aperture of a size on the same order as the wavelength of the light will be locally coherent. The phase of this locally coherent light depends upon the thickness of the transparent material through which the light passes; as such, phase shift photomask apertures have varying thicknesses relative to one another, to establish the phase shift relationship. The phase shift effect may be used to define extremely small features on the wafer by placing opposite phase apertures on opposite sides of the small feature to be defined. To the extent that diffracted light reaches the photoresist at the location of the feature from both of the opposite phase apertures, the opposing phases will tend to cancel one another. As a result, unintended exposure of critical feature locations is greatly reduced, permitting the formation of these features.
Examples of conventional phase-shift photolithography are described in U.S. Pat. No. 5,045,417, U.S. Pat. No. 5,573,980, and U.S. Pat. No. 5,858,580.
In particular, one conventional approach utilizes two masks in the photolithographic patterning of critical dimension features, such as polysilicon gate electrodes in integrated circuits. While the use of two photomasks, and thus two exposure steps, is of course cumbersome in the manufacture of integrated circuits, the incorporation of phase-shift masking for critical dimension features along with conventional masking for the non-critical dimension features, into a single photomask, has been found to be extremely difficult, and unsuitable for automated mask generation. The above-noted U.S. Pat. No. 5,858,580 describes a known two-photomask photolithographic process. According to this technique, one photomask, referred to as the xe2x80x9cphase shiftxe2x80x9d mask, defines the critical dimension features through the use of adjacent phase-shift apertures therethrough. These critical dimension features, in the case of the polysilicon gate level, are typically located over xe2x80x9cactivexe2x80x9d regions of the integrated circuit wafer, so that the patterned gate electrodes thereat serve as transistor gates. The other photomask, referred to as the xe2x80x9cbinaryxe2x80x9d mask, defines features of the level that are not critical dimension, and that do not require phase-shift masking; as such, the binary mask does not include phase-shift apertures. The binary mask also masks the phase-shift-exposed locations of the wafer, so as not to interfere with the phase-shift exposure of the critical dimension features. According to this technique, photolithography is carried out by exposing the wafer first through either the binary mask or the phase shift mask, and then (before developing the photoresist) again exposing the wafer through the other of the paired masks. As a result, the critical features are formed by way of phase-shift masking, while easing the generation of the photomasks themselves so as to comply with the design rules of the integrated circuit.
It has been observed, in connection with the present invention, that certain difficulties are present in the fabrication of integrated circuits using the two-photomask method, such as described by way of example in the above-noted U.S. Pat. No. 5,858,580. These difficulties will now be described relative to FIGS. 1a through 1f. FIGS. 1a and 1b illustrate, in plan and cross-sectional views, respectively, an exemplary structure to be formed at the polysilicon gate level in an integrated circuit, relative to which difficulties faced with conventional phase-shift photolithography will be described with reference to FIGS. 1c through 1g. This structure is formed at a surface of silicon substrate 2 at which field oxide structure 8 is present, adjacent to active region 4 at which transistors will be formed. As is well-known in the art, active region 4 is defined by those locations of the surface of substrate 2 at which field oxide 8 is not present, such that field oxide 8 serves as an isolation structure. Polysilicon gate electrode 6g and polysilicon conductor 6c are formed from the same deposited polysilicon layer, patterned by way of phase-shift photolithography as will be described below. Gate electrode 6g is of course disposed over active region 4 (separated therefrom by gate dielectric 7, in the conventional manner), and slightly overlaps onto field oxide 8; in this way, in operation, voltage applied to gate electrode 6g will control conduction between the opposing sides of active region 4 (which will be doped to form the transistor source and drain). Conductor 6c, in this location of the integrated circuit, is disposed on field oxide 8, and serves as a signal conductor. According to this example, gate electrode 6g is a critical dimension feature, meaning that it is to be formed to have a very narrow (e.g., on the order of 0.15xcexc) width so as to provide a high performance transistor. Conductor 6c, on the other hand, is formed of a non-critical width (e.g., 0.5% or greater).
FIGS. 1c and 1e illustrate portions of a pair of photomasks 13, 15 used to pattern gate electrode 6g and conductor 6c according to a conventional technique, similar to that described in the above-noted U.S. Pat. No. 5,858,580, for the case where positive photoresist is used (i.e., exposed photoresist to be removed in developing). As noted above, photomasks 13, 15 may either be reticles, or 1xc3x97photomasks. Typically, however, in modern photolithography of sub-micron features such as in this example, photomasks 13, 15 will be reticles.
Phase shift photomask 13, illustrated in FIG. 1c, utilizes the phase-shift technique noted above to pattern critical dimension gate electrode 6g. As shown in FIG. 1c, phase shift photomask 13 includes apertures 100, 10xcfx80, which are disposed on opposite sides of the location at which gate electrode 6g is to be formed. Apertures 100, 10xcfx80 are constructed so that they transmit light of opposite phase relative to one another.
FIG. 1d illustrates, in cross-section, the portion of phase shift photomask 13 that includes apertures 100, 10xcfx80. Phase shift photomask 13 includes quartz substrate 11, upon which chrome film 9 defines the location of apertures therethrough, such as apertures 100, 10xcfx80. According to this conventional approach, apertures 100, 10xcfx80 are realized not only by the absence of chrome film 9, but also by the depth to which a recess or trench is etched into quartz substrate 5 thereat. In this example, aperture 10xcfx80 is formed by a recess etched into quartz substrate 11, while aperture 100 is simply an opening in chrome film 9. The depth of the recess of aperture 10xcfx80 is selected so that the remaining relative thicknesses to, txcfx80 of substrate 11 at apertures 100, 10xcfx80, respectively, correspond to the desired relative phase of light passing therethrough (considering the transmitted light to be locally coherent, as noted above). These thicknesses t0, txcfx80 depend upon the wavelength of the light to be used in the exposure, as is known in the art. In this case, the light transmitted by aperture 10xcfx80 will have a 180xc2x0 (xcfx80 radians) phase shift relative to the light transmitted by aperture 100.
Referring back to FIG. 1c, phase shift photomask 13 does not expose photoresist at any other locations than at the critical-dimension locations, according to this conventional approach. In particular, it is apparent from a comparison of FIG. 1a to FIG. 1c that phase shift photomask 13 does not expose the region between gate electrode 6g and conductor 6c, nor does it expose much of active region 4 on either side of gate electrode 6g. As such, phase shift photomask 13 is typically referred to as a xe2x80x9cdark fieldxe2x80x9d mask. According to conventional two-mask phase shift photolithography, phase shift photomasks such as photomask 13 do not have apertures that are not directly over active regions, such as active region 4.
Binary photomask 15 exposes photoresist regions at the non-critical dimension locations of the integrated circuit, as evident from FIG. 1e. In this example, binary photomask 15 includes chrome regions 12g, 12c that mask exposure at the locations of gate electrode 6g and conductor 6c; photomask 15 is transparent at the other regions, and as such is commonly referred to as a xe2x80x9cbright fieldxe2x80x9d or xe2x80x9clight fieldxe2x80x9d photomask. Chrome region 12g operates as substantially a gate protective mask, and is not formed to the critical dimension; rather, chrome region 12g simply protects the region of photoresist that has been, or will be, exposed through photomask 13 from additional exposure, relying on phase shift photomask 13 to define gate electrode 6g. Chrome region 12g does, however, define the end of gate electrode 6g that extends toward conductor 6c, considering that adjacent 0xc2x0 and 180xc2x0 phase shift apertures could not so define an exposed region (because of the phase cancellation effects). Chrome region 12c defines conductor 6c, as this feature is not of critical dimension.
In the manufacture of the structure of FIGS. 1a and 1b, as is well known in the art, a photoresist layer (positive resist, in this example) is dispensed over the previously deposited polysilicon layer from which gate electrode 6g and conductor 6c are to be formed. The wafer and photoresist will then be sequentially exposed to light of the desired wavelength (e.g., ultraviolet) through photomasks 13, 15. As described in the above-noted U.S. Pat. No. 5,858,580, the order in which photomasks 13, 15 are used is not important. Following this second exposure, the photoresist layer is developed, with the locations of photoresist that were exposed through photomasks 13, 15 being removed, and the unexposed regions remaining to serve as a mask for etch of the polysilicon. A common problem encountered in photolithography is the presence of low contrast regions of the pattern, such as between gate electrode 6g and conductor 6c in this example, at which bridging of the etched polysilicon may result. FIG. 1f illustrates the results of a simulation of the magnitude of light exposure for the case of double exposure through photomasks 13, 15, as described hereinabove. In this particular example, the critical dimension width of gate electrode 6g is approximately 0.16xcexc, and the space between the end of gate electrode 6g and conductor 6c is approximately 0.12xcexc, as evident from FIG. 1f. 
FIG. 1f illustrates that the central location at which gate electrode 6g is to be formed receives no light exposure, nor does the location of conductor 6c (the no exposure regions represented by the cross-hatching). Locations on either side of the location of gate electrode 6g receive full exposure (indicated by the absence of hatching). FIG. 1f also includes contour lines, each representative of locations receiving common exposure levels, and each corresponding to a 10% step from full exposure to no exposure. As evident from FIG. 1f, the region between the end of gate electrode 6g and conductor 6c does not receive full exposure as it ought to (polysilicon is to be etched from this location, as shown in FIG. 1a); rather, this region receives on the order of 60% of full exposure. This reduced exposure is due to the small spacing between chrome regions 12c, 12g of binary photomask 15. Because of this reduced exposure, some amount of photoresist may remain at this location after exposure and developing, particularly considering such factors as photoresist thickness and topography due to field oxide structure 8 at this location. As a result, the etch of polysilicon between gate electrode 6g and conductor 6c may be incomplete, causing bridging and shorting between these two elements. Because conventional double photomask phase shift lithography has been concerned with the definition of critical dimension features such as gate electrode 6g, this conventional approach does not provide relief for this problem.
By way of further background, phase shift masks having opposite and intermediate phase regions are also known in the art. FIG. 1g illustrates phase shift photomask 17 according to this conventional approach, for the example of the structure of FIGS. 1a and 1b. As shown in FIG. 1g, photomask 17 includes chrome regions 16g, 16c, that mask the locations at which gate electrode 6g and conductor 6c are to be formed. Apertures 18 in photomask 17, however, have one of four possible phase shifts, and are arranged so as to provide phase cancellation at the critical dimension of gate electrode 6g, while permitting exposure of the end of gate electrode 6g that extends toward conductor 6c (FIG. 1a). In the example of FIG. 1g, apertures 180, 18180 are on opposing sides of chrome region 16g, and transmit opposite phase light relative to one another. On the end of chrome region 16g toward chrome region 16c, however, photomask 17 includes adjacent apertures 1860, 18120, which transmit light at 60xc2x0 and 120xc2x0 phase angles relative to the light transmitted through aperture 180. Aperture 1860 is disposed between apertures 180 and 18120, and aperture 18120 is disposed between apertures 1860 and 18180, as shown in FIG. 1g. While this gradation of phase shift through apertures 18 provides adequate exposure, in many cases, for structures such as that shown in FIGS. 1a and 1b, such multiple phase photomasks are extremely expensive to fabricate, are not conducive to automated photomask generation, and also present significant difficulty to focusing of the exposure in the photolithography process.
It is therefore an object of the present invention to provide a photolithography method in which critical dimension features may be fabricated in close proximity to other features, while providing adequate exposure therebetween.
It is a further object of the present invention to provide such a photolithography method which utilizes a pair of photomasks for the exposure.
It is a further object of the present invention to provide such a photolithography method which does not require more than opposite phase apertures.
It is a further object of the present invention to provide such a photolithography method in which the fabrication of small features is improved.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented in a two-photomask system for exposing photoresist in the photolithography of a single functional level in an integrated circuit. One photomask serves as the binary photomask, and includes masking structures that mask the exposure of non-critical dimension features, as well as protecting critical dimension features from exposure. The phase shift photomask includes opposite phase apertures for the exposure of critical dimension features. Additionally, the phase shift photomask includes additional, non-phase-shift, apertures corresponding to locations at which inadequate exposure is possible, such as at locations between adjacent structures.